Many opportunities and problems became highly interlinked in 2025, fueled by the historic growth in everything AI. But how close are we coming to breaking points, and what are people doing to mitigate them? That is the story that will unfold this year.
AI’s penetration into an increasing number of workloads is placing almost quadratic demands on compute, memory, interconnect, and the architectures that bind them. Data center designs are evolving, moving beyond just performance considerations of GPUs. Issues such as power and thermal are becoming primary design considerations all the way from microscopic levels up to the national level and beyond. AI is causing changes, and it is increasingly helping to make those changes.
2026 could be a pivotal year, especially as we start to see production limitations and shortages develop in both semiconductor fabrication and packaging at the most advanced nodes, and limitations in the availability of memory. We also could see a broader range of companies benefit from the vast investments made by those on the cutting edge, which will be vital if inference is to move out of the data center and into the edge.
Continued development in AI
Ask a dozen people to name the most significant limiter for AI, and you will get two dozen answers. Some of these are related to geopolitics, controls on technology, or business issues, and we generally ignore those because nobody is willing to go on record talking about these anymore. But there are many technical issues that people are willing to discuss, including memory availability and bandwidth, interconnect standards, the need for new and more specialized data models, better security, and changing pressures from inference, among others.
“The biggest roadblock today isn’t the compute,” says Barun Kar, CEO of Upscale AI. “It’s the networking portion. Systems can’t move data fast enough between the GPUs to keep up with AI scale and speed. What exists today are proprietary, closed technologies, and this is making things more expensive and inflexible. The industry needs open standards so that any compute vendor, if they adhere to the open standards, can connect seamlessly.”
As companies start to rely on AI-based solutions, secondary issues become important. “Memory safety is becoming a primary design requirement,” says Jeff Wittich, CPO at Ampere Computing. “The scale and sensitivity of today’s AI workloads mean that vulnerabilities once considered niche can now have widespread impact. As organizations run high-value models concurrently, the risks of memory corruption, data leakage, and exploitation increase sharply. In 2026, we expect memory-safe compute to move from an optional enhancement to a standard requirement, particularly for mission-critical AI operations. This year marks a turning point as memory integrity becomes a core expectation for any infrastructure built for AI at scale.”
The major driver has been large language models, but these are not ideal for many applications. “We are seeing a lot more research in small language models, or domain-specific models,” says Sathish Balasubramanian, head of product management and marketing for AMS at Siemens EDA. “They are focused on training, taking a very simple open-source model with 70 billion parameters, and then fine-tuning it for the semiconductor domain. As the foundation models are getting smarter, people know how to build special models, or small language models. We are seeing an increasing focus on inferencing.”
As the focus turns towards inference, design issues change. “Inference adds further pressure with low-latency, high-volume traffic from users worldwide,” says Upscale’s Kar. “Basically, your network has to evolve into a high-performance, software-defined fabric that is optimized for AI data centers and scale.”
The whole problem is becoming software-defined. “We see a lot of custom designs being built for specific applications,” says Siemens’ Balasubramanian. “Everything is going to be based on your workload or the end application, and then the software that determines the architecture decisions, the PPA metrics that are appropriate, or what process or tech node they need to focus on. We are seeing more shift-left decisions being made, and that gives a lot more customization to workloads. We’re seeing a lot more design starts.”
Each workload has different needs. “Enterprises are rapidly expanding the range of AI workloads they run in production,” says Ampere’s Wittich. “According to a recent McKinsey survey, more than two-thirds of respondents say their organization is using AI in more than one function. This expanding variety highlights that AI workloads cannot be served effectively by a single type of compute. Each category of model — and even each individual component of a model — has distinct needs around memory, latency, cost, and throughput.”
As some of those workloads become more stable, new types of optimization become viable. “We see people wanting to move away from homogeneous architectures,” says Kar. “Today, people are locked into a single vendor because no one can interact with each other. If you want to do something different for pre-fill versus decode, use different hardware for one versus another, or if you want to do a hybrid design, that’s not possible. With the advent of things like ESUN and UAlink, you can mix and match. You might have one piece of hardware that is better for certain things, and if you couple that with a different piece of hardware, you might get better tokens per second. There are software programs in development that can enable these things.”
This could be a key change for 2026. “Agentic systems accelerate this shift because they involve multiple tasks working together with different resource profiles, making it harder to rely on a single type of hardware or uniform infrastructure footprint,” says Wittich. “In 2026, heterogeneous compute will become a defining characteristic of enterprise AI infrastructure as enterprises adapt to the widening spectrum of workloads they need to support, and the mixed nature of the tasks required within the workload.”
Data centers also are being impacted by more widespread adoption. “Security is a big deal,” says Niels Faché, vice president and general manager of Keysight EDA. “Customers want to run all of their tools within their own firewall. When we rolled out our first chatbot, which was hosted by Keysight, it went through customers’ firewalls, and that did not work for everyone.”
“Rising AI demands, the need for performance consistency, long-term cost control, and stricter data requirements are pushing enterprises to rely more on infrastructure they directly control,” says Wittich. “Instead of depending exclusively on large, centralized clouds, companies are building out regional data centers, co-location footprints, and specialized on-prem deployments that are optimized for AI inference and emerging agent workloads. This reflects a more balanced approach, in which enterprises blend cloud capabilities with dedicated compute resources they operate directly to place workloads where they run most efficiently and predictably. In 2026, we expect this blended strategy to mature as organizations refine infrastructure models that use both cloud and owned compute in complementary ways, allowing them to meet rising AI demands with greater stability and flexibility.”
More power needed
During 2025, many alarm bells started ringing about power. This concern is at the die level, the package level, as well as the board, rack, data center, and grid levels.
Many AI chips are limited by thermal considerations due to energy dissipation within chips, while at the same time, fabrication and packaging densities are increasing, resulting in higher power densities. This is causing a reconsideration of design practices that previously were thought to be too difficult.
“If we look at how crypto came into being, it went from CPUs, to FPGAs, to GPUs, to dedicated chips,” says Kar. “All of that was to reduce power and improve performance. Near threshold voltage is one way to achieve that. You’ll see a similar trend happening in the AI space. In order to adhere to these power needs or power bottlenecks, you will see those technologies come into play for AI workload-specific ASICs, as well as low-voltage ASICs.”
From the printed circuit board down to the die, power delivery networks are being examined closely. “Different architectures are emerging,” says Shekhar Kapoor, executive director for product management at Synopsys. “When you convert 48 volts to 1 volt, or for the data center, pushing hundreds of watts into a single port, you need to have power delivery very well planned. How are you going to get from voltage regulators to embedded voltage regulators, which themselves are going to be stacked. The PMIC methodology is shifting from a general consideration of doing an advanced package design with an interposer, to a methodology where you address the performance per watt and reliability aspects of it. You can stack as much as you want, but if you do not have a plan, you are heading for problems.”
One of the first considerations for locating a new data center has become securing adequate power. “Advancing toward artificial general intelligence (AGI) will require significant compute power, efficiency, and energy solutions,” says Wittich. “The models emerging today require far more sustained compute than previous generations, along with reliable access to the power needed to operate them. What began as a rapid uptick in investment throughout 2025 is not slowing down in 2026. This next phase of AI development brings a new level of urgency as enterprises and cloud providers expand capacity to support larger models, faster iteration cycles, and new forms of agentic and autonomous systems. In 2026, the race is about securing the compute and power infrastructure required to keep pace with an increasingly advanced generation.”
New technologies
AI will dominate the semiconductor industry news cycle in 2026, much as it did in 2025, leading to more changes and disruptions. “The industry will continue to grow at a pace enabling it to reach $1 trillion by, or even before, 2030 with the aid of AI in every facet of business and technology,” says John Kibarian, CEO of PDF Solutions. “This fast AI-enabled growth comes with challenges — the complexity associated with advanced 3D packages and systems design and manufacturing, managing global supply chain complexity, and improving operational efficiency. We already see signs of combined industry-wide collaborative relationships between design and manufacturing that leverage AI-based predictive analytics for boosting operational efficiency and smarter decision-making.”
What started as a custom solution for each large customer is beginning to get consolidated. “Look at TSMC with the COUPE flow for 3D IC,” says Balasubramanian. “The methodologies and techniques that were developed and customized for one big customer, then customer two, are being standardized into the ecosystem. We are at that stage where it’s going to go mainstream. 3D IC is mainly focused on hyperscalers and the top three or four semiconductor companies who are using it – because it’s very complex and they have the money, they have the demand, and they have the SKUs that support that investment. But that is now getting trickling down to other customers. This year is going to be a big year for 3D IC, where it’s going to transition to mainstream.”
Synopsys’ Kapoor confirms this. “Last year, we said 50% of high-performance computing design would be multi-die, and that has materialized. For 2026, we expect that will grow another 20% to 25%. The reason is pretty simple. The big driver has been training in the data center, and that is turning toward inference. When you start throwing in more videos and more agentic applications, having trained all these models, you need the ability to re-load this information and infer from it.”
Some designs will migrate in-house. “A lot of the second-tier vendors, who may not have the size, expertise, and deep pockets of the leading guys to attack 3D-ICs, have been working through ASIC vendor type arrangements,” says Marc Swinnen, director of product marketing at Synopsys. “These arrangements allowed them to have the chips done for them, or at least the last stage of physical design. That will start migrating into their own teams. You’ll see a continued steady adoption. A lot of these companies have pilot projects with one or two chiplets assembled together. That will continue to increase. The benefits are just too great.”
While it may not happen in 2026, we also can expect additional application areas to start moving in this direction. “We are seeing AI or genAI capabilities coming into the mobile phones,” says Balasubramanian. “Once they have the requirement that they need to have these models — everything within a system, within a mobile phone — then they need to have enough high-bandwidth memory. They need to have enough processing power. All of that must be within the limits of real estate, and that will drive them towards 3D-IC. But the cost factor also comes into account. It needs to be cost-friendly for their end customers to actually adopt it. That’s the whole idea of mainstream usage. It slowly trickles down from advanced node and advanced technologies of major customers to the consumer side. That will probably be within the next couple of years.”
There may be additional challenges that need to be overcome before they can fully adopt the technology. “A product in the mobile space has other components they have to deal with, such as basebands,” says Kapoor. “They would be looking at 3D heterogeneous integration. Inference is one thing, which may be their driver. But they have to enable, from a networking or communications point of view, other aspects, as well. Heterogeneous doesn’t just mean that you need different process nodes. It is digital and analog, which will be part of the same package.”
The integration of optics with semiconductors has been around for a long time, but it’s always been too expensive, too complex, or too niche in its application. “Co-packaged optics has finally come to the point where it’s starting to be adopted for more mainstream and broadband applications, especially with the data centers driving the communication backplane between the data centers,” says Synopsys’ Swinnen. “It enables you to get the communication between them fast enough, and low power enough, that they act as if they were one giant chip. By using optical connections between the boards, it makes less difference whether they are processors on the same machine or on different machines. You bring machines closer together with high-speed interconnect.”
New analysis
The migration to advanced packaging and assemblies has brought with it new physical issues that need to be understood. “The applications are becoming more complex, and you can’t talk about an application being purely electrical,” says Keysight’s Faché. “It’s about circuit physics, and maybe semiconductor physics, or it’s mechanical. A lot of the applications are now multi-physics, and we know, for example, all about the thermal issues — especially when they’re working on chiplets. When you look at server racks, massive thermal issues cause mechanical stress. You now need to do vibrational analysis on electronic systems. We’ve migrated from a world where you could look at one engineering discipline at a time. Now we live in a world that is about multi-physics and the need to coordinate multiple engineering disciplines, from product design to product performance to reliability and manufacturability.”
This is going to create some interesting partnerships. “You’ll see some surprising solutions where unusual combinations of companies will come together, because of the breadth of the solutions required,” says Swinnen. “You’ll see some announcements being made where companies that traditionally didn’t play in both multi-physics chip-to-system solutions are looking for this chip-to-system solution. That should be interesting from the business side.”
Faché sees a similar trend. “It’s a multi-engineering world, and so you have to make sure that these workflows are all interoperable. That brings with it a number of challenges. You have to bring different tools, potentially from multiple vendors, together into one workflow. Interoperability between tools is absolutely important. We’ll see a shift from what sometimes are monolithic tools, where you have one platform, one tool, and everything must happen in that environment.”
We have already seen some high-profile examples. “The industry leaders are not only investing in these companies for the sake of growth. They want to get the technology they are investing in for the technology itself,” says Kapoor. “You want to tap into that technology. It’s just a broadening ecosystem beyond the traditional ‘secure your foundry capacity’ into ‘how can I build a competitive advantage by partnering in some way?’ What started in 2025 is not the end of it. There will be more in the coming years.”
Some issues need increasing levels of research. “People with a focus on semiconductor are realizing that domain knowledge and the expertise and basics of sciences are getting more important — physics, electrical engineering, electronics,” says Balasubramanian. “We are seeing a lot more research happening on AI, but focused on semiconductor research, semiconductor design, and manufacturing happening in the universities. There is a groundswell for getting good people trained.”
There is a talent gap that needs to be filled. “AI is going to allow experts to be experts and spend less time dealing with the intricacies of running tools,” says Faché. “Instead, they can focus on requirements management and design. That is a shift in the work of product development teams. At the same time, the specialization continues to go up. It’s very difficult for a company that is designing a complex product to hire talent in the open market, unless they can hire from someone who is in their space. There’s going to be a lot of emphasis on internal development of talent and internal training. You can hire good people from universities, but they’re still novices, and a lot of companies depend on critical talent, and so they will nurture that talent in-house.”
Bringing people up to speed has become key. “In an IBS study, the industry is willing to hire around 100,000, but can’t find enough people,” says Balasubramanian. “People are coming in, new grads are coming in, but they need to focus on how to get ramped up. That’s the whole idea of agents. They won’t solve 100% of the problem, but if you solve the 20% of the problem that consumes 80% of the time, they can focus on the rest of the things, either to make better designs, the same design faster, or work on multiple projects.”
While some of these problems are causing delays and respins, functional verification continues to be the primary reason why chips are failing at an increasing rate. “Tools become better, and that allows customers to handle more complex problems,” says Faché. “There are end-market requirements that drive complexity, and they depend on better tools. It’s that constant interaction. There’s always going to be a problem space where you feel like your most complex problem cannot be handled as well as you would like.”
There are two reasons why chips fail, functional or physical. “Physical is a lot more regulated in terms of rules. It’s much more constrained with all the foundry PDKs,” says Balasubramanian. “Functional failures are where most of the issues happen. There is an increasing focus on software development early in the chip design cycle, so that the software stack works very closely with the hardware stack and you cover all the corner cases. This is causing an increased demand for emulation.”
That may work for digital design, but struggles in more heterogeneous systems. “If I look at our company, we design hardware, we sell instruments,” says Faché. “We have very complex radios in some of these instruments. We don’t design our chips in one turn. It takes several turns. And we’ve been at this for decades, using our own design tools. We’re very good designers, and we use best-in-class practices. It’s hard for us to get it right the first time. With 6G radios, if you go over 100 gigahertz, that creates a whole set of new technological challenges. You have different packaging technology, so the complexity is different. You’re always dealing with new frontiers of technology, and the tools are enabling that. But it’s a constant race to make sure the tools can cover the complexity that customers deal with.”
Design practices
AI will require new design tools and flows, but it also will also enable them. “In 2026, AI’s influence in design will expand both vertically and horizontally,” says William Wang, CEO of ChipAgents. “Vertically, we’ll see AI-driven EDA evolve beyond the front-end and back-end stages, enabling more automated and optimized full RTL-to-GDSII flows. Over time, AI agents will begin to unify feedback loops from post-silicon validation back into pre-silicon design, closing the gap between simulation and real-world performance. Horizontally, AI will extend its reach from digital design into analog and mixed-signal domains, where data scarcity and complex interactions have historically limited automation. Together, these advances will reshape how designs are conceived, verified, and iterated, moving toward a truly intelligent, end-to-end design ecosystem.”
While the impact of some AI tools has been disappointing, the productivity boosts within many EDA flows is large. “Agentic AI is going to revolutionize simulation,” says Matt Commens, director of product management at Siemens. “2026 will be the year when it really comes out big. We already have some partners and companies building agentic workflows. It’s going to take out all the mundane things we ask users to do and let them focus on design instead of simulation parameters. It is going to exponentially grow the amount of simulation that can be done. It will make software more accessible to engineers, no longer just the guru who can fully leverage the technology. We always talk about simulation time, but a lot of time goes into setting up the simulation. That time can be more than simulation, and that time is going to get shrunk by a lot.”
Companies will need to be agile if they want to fully take advantage of these changes. “Design houses will have to reorganize around AI-augmented flows, like AI copilots, agents for implementation, verification, and debug,” says Kar. “Next year, two things are going to happen. One is to raise output per engineer — that is, productivity — and the second thing is to improve quality. More end-to-end platform integration with tight simulation iteration will push teams toward a more holistic co-design with fewer tool silos. The competitive edge will tilt toward people who can implement operational learning loops. ‘Can we capture design and verification to continuous retrain models, which would improve quality?’”
Models of all types become increasingly important. “We can think about building AI generator models, and we can run physics-based simulations, which can take a lot of time,” says Faché. “Think about a thermal analysis and electromagnetic analysis simulations. They can take hours. And when you’re optimizing, you’re doing this many times over. But if you do this up front, you can build surrogate models, response services, and now you use those in simulations that can really speed up the design and simulation process, as well.”
Methodology improvements have been significantly impacted by the lack of models. “If you create models by hand, you will always lose in terms of time,” says Roland Jancke, head of department design methodology at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “It is too slow. But those models are required for early evaluations and systems engineering. So how can you generate those models out of a generic system description, out of a specification, out of the requirements or something? This is the key for the future. You need to find a mechanism that creates those models out of human descriptions of what needs to be built. That’s how AI will help in the development process.”
If you can learn from what has been done in the past, you can build new tools that solve problems. “Shift left is powered by an abstraction of problems, from the physical domain,” says Prakash Narain, CEO of Real Intent. “They show up because of these new technologies. If you have a problem in the physical domain and you want to have a predictable design process, you have to bring that problem into the functional domain and make sure you have robust design techniques that will prevent those problems from occurring in the design. The understanding and the modeling of those problems, and the solutions, get brought back into the functional domain.”
This will require all EDA companies to create open interfaces. “AI is a layer on top of existing tools,” says Faché. “Most customers want to combine different tools, add some of their own capabilities, and they need standardization around design practices, rules, and languages. For example, when it comes to languages, we are all using Python today. As more customers create Python-based workflows, they need to be able to infuse AI into that.”
No one company will be able to do it all. “Phase one was more about targeted optimizations and reaching a desired PPA in the fastest possible time,” says Balasubramanian. “The second wave is a more general productivity improvement, focused on achieving an outcome. It will address the issue, ‘How can you become more productive if the complexity is increasing, when your market window remains the same?’ That’s where these assistants come into the picture. We are moving into the world of assistants, and for 3D-IC it will even be an enabler. In the past, you had to deal with many tools, many pieces, and this would help to bring them together.”
RISC-V
While developments around the RISC-V processor have slowed a little, that is only because it has now evolved to a point where people can use it, gain experience with it, and slowly add that feedback into the development process. “We are already seeing a rise in real workload silicon — the creation of devices that target specific workload processing,” says Dave Kelf, CEO for Breker Verification Systems. “RISC-V is tailor-made for this purpose, given its open ISA. This allows the more traditional processor plus separate accelerator on a bus architecture to be replaced by a single core that contains the required data processing and control in one unit, with custom instructions to match. This trend will become evident in 2026 and will drive new system-level verification requirements, along with the potential for AI to read a workload spec and design the system around a fixed platform.”
RISC-V is catching up with the competition. “We believe RISC-V is going to go bigger, especially with geopolitics,” says Balasubramanian. “People love open source, and open source at some point wins. Right now, we see RISC-V keeps getting better. RISC-V is in the same stage where ARM architecture was five to seven years back — promising, but not as powerful or as good as x86. That’s what everyone is saying. It just took some time. We are at that crux of RISC-V getting mature faster. It’s going to get bigger. That’s not going to stop. We are going to see a lot more design starts.”
Related Reading
2025 – A Year Of Change And Anticipation
Unexpected change rewards those who are quick to adjust, but all aspects of a system must be adjusted to keep growth going.