A CMOS integrable RRAM technology should fulfil all CMOS bound requirements, in addition to being able to demonstrate any desirable technology driven specifications. A key requirement is that the devices are fabricated using CMOS compatible and transferable processes, enabling to transition from R&D to volume production. Additionally, the programming and electroforming voltages of the devices should be below the supply voltages of the target CMOS node. Device specifications should be drawn from the merits of the technology, while the process of deriving the specifications should be constrained to the CMOS bound requirements.
In readiness for the full integration cycle, the initial development of our RRAM technology is performed on 150 mm (thermally oxidised) silicon wafers. This is highly beneficial for early-stage development purposes, where material-based rapid-prototyping and technology characterisation performed directly on fully functional CMOS wafers could be cost-prohibitive and potentially hindered by the complexities of the integration process. The design follows a two-terminal metal-insulator-metal architecture, and the fabrication process uses standard contact photolithography for pattern transfer, while metallisation (bottom and top electrode (BE/TE)) and active (resistive switching) layer deposition are performed by e-beam evaporation, sputtering (including reactive) and atomic layer deposition (ALD). All device layers are defined either by photoresist lift-off or reactive ion etching (RIE). An optical microscopy image of a standalone RRAM and its corresponding cross-sectional schematic (dotted line through device) can be seen in Fig. 1a. The RRAM cells are laid out as 32 standalone devices per chip (3 × 3 mm) or alternatively as 32 × 32 crossbar arrays, as shown in Fig. 1b, with each chip comprising devices of a single dimension. The selected active area device dimensions range from 60 × 60 μm2 down to 1 μm2, with the smallest being a representative critical dimension (CD) of CMOS integrated RRAM. The chip layouts are repeated across the wafer, allowing for high-throughput, full-wafer (1000’s of devices) characterisation, when measured with a semi-automated probe system that is interfaced with an Arc ONE instrumentation platform34.
The alternative text for this image may have been generated using AI.a Optical microscopy image and cross-sectional schematic of a standalone RRAM (dotted line through device). b Optical image of a 32 × 32 crossbar array, 3 × 3 mm RRAM chip. c Electrode and active layer material library and their deposition methods
We have previously utilised a variety of materials and deposition techniques for fabricating and characterising metal-oxide RRAM devices, aiming to further understand the mechanisms that support resistive switching and ultimately to optimise the performance and enhance the reliability of the technology. Previous work spanned from identifying the conduction mechanisms of the well-received Pt/TiO2-x/Pt stack35, to exploring active layers such as SnOx36 that have received less attention, in addition to demonstrating the benefits of bilayer configurations such as AlxOy/TiO232 and HfO2/Ta2O537 and finally selecting appropriate electrode materials and identifying their interfacial characteristics, as they also hold a significant role for device performance38. Figure 1c summarises our electrode and active layer material library and their deposition methods.
A technique that we have previously explored39 and has received attention as a means of improving the electrical characteristics of RRAM is the introduction of dopants in the active layer. The technique is applicable for lowering the electroforming voltages, which not only minimises the risk of irreversibly damaging the devices during the forming process, but crucially could allow devices to operate within the voltage limitations of the CMOS technology. For the development of an integrable RRAM we have selected nitrogen as the dopant, while considering the well-established and characterised titania26,40 and hafnia41,42 films as reference. TiOxNy films were deposited using DC magnetron sputtering from a 99.995% titanium target either in an Ar rich plasma with N2 and O2 reactants or in a N2 rich plasma with the addition of O2 as co-reactant. The film that displayed the most suitable active layer characteristics was sputtered in an N2 rich plasma at 500 W power, 1mT process pressure and N2/O2 gas flows of 20/5 sccm, respectively (0.02 nm/s deposition rate). The active layer (25 nm thickness) was interfaced with Pt electrodes, and the fabricated devices required both lower forming ( ~ 6.5 V) and switching voltages ( ~ 1 V) in comparison to their TiOx counterparts ( ~ 9 V and ~1.5 V, respectively). The HfOxNy films were synthesised by thermal ALD using tetrakis dimethylamido hafnium IV (TDMAHf) as the hafnium source, N2 plasma as the nitrogen source and either H2O or O2 plasma as the oxygen source. The film with the optimal active layer characteristics was synthesised at 250 °C, using TDMAHf, H2O and N2 plasma (5 sccm N2 gas flow) at 300 W. In comparison to any titanium- or hafnium-based oxide and oxynitride variants explored, the devices fabricated using this HfOxNy composition as an active layer (10 nm thickness) when interfaced with TiN electrodes, were found to display the most favourable electrical characteristics for a CMOS integrable RRAM. This included low forming ( ~ 2–4 V) and switching voltages ( ~ 1–3 V), with gradually quasi-analogue tuneable resistance.
CMOS electronics and wafer-level post-processing
Several IC designs were taped-out based on a systematic increased complexity approach that followed the development cycles of the integration processes. Initial designs focused on simple test structures for process control and small memory arrays, followed by efforts on array up-scaling and finally complex array designs and new concepts based on RRAM technologies, such as sensors, neural networks and adiabatic memories. Custom CMOS electronics were sourced from a silicon foundry and fabricated on 200 mm wafers (Fig. 2a), using a 1P5M 180 nm process (1.8/5 V supply voltages), with the option to end the fabrication process at metal-4, followed by deposition of what would normally be an interlayer dielectric (ILD) and finally planarisation.
The alternative text for this image may have been generated using AI.a Photograph of 200 mm foundry fabricated CMOS wafer. Inset shows an optical microscopy image of a multi-design reticle. b Foundry passivation is initially thinned by blanket wet etching. The representative profilometry scan (and corresponding optical image) of a section of the partially etched CMOS passivation reveals an etching-induced, topology-heavy wafer surface. c Final passivation thinning and re-planarisation by CMP. A representative AFM scan of a section of the re-planarised wafer surface, with the matching layout of the underlying metal layer
The integration methodology detailed in this article is applied to the metal-4 version of the CMOS wafers, where the ILD-4 stack acts as the passivation layer and comprises ~650 nm thick SiO2, capped by ~200 nm thick Si3N4. These materials and thicknesses are considered typical across the discussed technology nodes and prior to the industry shifting to low-k carbon-doped SiO2 based dielectrics for the 90 nm node and below. To minimise the integration complexity, particularly for high-density architectures, the foundry passivation was then thinned down to ~100 nm by a means of etching and re-planarisation. First, a foundry-spun protective photoresist layer was removed using N-Methyl-2-pyrrolidone (NMP) at 65 °C, followed by a 30 min O2 plasma at 350 W and 800 mT process pressure. The wafers were then blanket etched using 5% hydrofluoric acid (HF) with an observed 1:2 Si3N4/SiO2 etch selectivity, that reduced the passivation thickness to ~ 200 nm SiO2. It would be anticipated that this wet etch method would result in a thinned passivation with no significant local non-uniformities. However, the etched-surface topology was modified significantly matching that of the underlying metallisation pattern as can be seen from the profilometry scan and the corresponding optical image in Fig. 2b. While the cause of this effect is unclear, it may be the result of some form of local metal migration in the dielectric, which is likely to be dominant in the proximity of the two-layer interface. Therefore, although the etch may initially be uniform, as the passivation is progressively thinned, the etch rates for areas with and without underlying metallisation differentiate representing a local difference in material composition. Chemical mechanical polishing (CMP) was then employed to further thin the passivation and re-planarise the wafer surface. CMP was performed with a colloidal silica slurry, while the polishing pad was re-dressed at regular intervals. Platen and polishing spindle speeds were set to 35 and 30 rpm respectively, while the downforce pressure was set to 90 kPa. Post-CMP wafer cleaning was done in a 0.4% trimethylanilinium hydroxide (TMAH) solution with ultrasonics, followed by ultrasonics assisted soaking in de-ionised (DI) water at 65 °C, spin drying and finally O2 plasma clean-up. Figure 2c shows an atomic force microscopy (AFM) scan of a small section of the re-planarised wafer surface with a calculated mean roughness (Sa) of 0.21 nm and root mean square roughness (Sq) of 0.31 nm. The matched layout of the underlying metal layer is also shown, confirming a significantly reduced topology. Both reduced surface topology and roughness are favourable characteristics of the thinned CMOS passivation, with the first primarily minimising the photolithographic complexities of the RRAM integration process and the latter minimising any possible influence to the conduction mechanisms of the integrated devices.
We have previously demonstrated a methodology for adding functionality to foundry produced CMOS at singulated chip level43. Wafer-level post-processing, combined with stepper photolithography positions itsself at the opposite end of the integration spectrum. Both options are defined by merits and drawbacks, that are tied to cost of operation, complexity of processing technologies and speed of development cycles. For the work presented in this article, we have taken an approach that meets these options in the middle. Therefore, post passivation thinning, the CMOS wafers are diced into larger sized chips comprising the full reticle replicated several times. Although process equipment are normally set up and optimised for full wafer processing, the selected chip size offers adequate processing compatibility (no mounting on carrier substrates is required) and, when combined with direct-write photolithography or e-beam lithography is ideally suited for enabling a fast development route towards a CMOS integrated technology, where both integration processes and integrated devices can be characterised using a reasonable number of nominally identical samples. This is supported by the proposed lithographic options that allow for straightforward modification of designs should layout patterns need to be revised, while their slow exposure speed (particularly at high resolution) is practically not applicable when patterning at the proposed scale.
Multi-reticle CMOS-RRAM integrationIntegration development: small-scale arrays
Early-stage integration focused on a small array design, where RRAM devices were integrated to the CMOS BEOL to realise a 16 ×16 one-transistor-one-resistor (1T1R) crossbar array. With no added complexities arising from standard CMOS electronics, the selected design is ideally suited for the development and characterisation of the core integration processes, while process compatibility with CMOS can be verified with an electronically functional integrated array. A summary of the proposed RRAM integration process is schematically presented in Fig. 3. Briefly, the foundry passivation (Fig. 3a) is initially selectively etched to expose the top CMOS metallisation (Fig. 3c). This is followed by patterning of the RRAM stack (Fig. 3e, g and i) and finally the etched trenches are metal-filled to ensure good connectivity between RRAM and CMOS BEOL (Fig. 3k). The adaptation of this pseudo-via approach eliminates the need for establishing damascene and metal CMP during early-stage development, while these wafer-level-only processes can be incorporated at a latter phase, when integration transitions to volume fabrication lines. Figure 3b shows an optical image of a section of the foundry produced CMOS array. Each column in the array comprises a wide metal-4 track serving as a connection placeholder for the TE of all RRAM devices in a column (bit-line), while each row consists of small metal islands that are interconnected to the drain of pMOS FETs and also serve as individual connection placeholders for the BE of each RRAM in a row.
The alternative text for this image may have been generated using AI.a Cross-sectional schematic of foundry produced CMOS BEOL. b Optical microscopy image of foundry fabricated CMOS array (part of). c Selective passivation etch (vias). d Optical image of the passivation openings (inset shows SEM imaging of trench profile). e RRAM BE deposition and patterning. f Optical image of 2 μm TiN BEs. g RRAM active layer deposition and patterning. h Optical image (post dielectric deposition) with overlayed mask (yellow) of active layer via-etch (insets show UV images of the re-opened vias). i RRAM TE deposition and patterning. j 16 × 16 array (part of) with 2 × 2 μm2 TiN/HfOxNy/TiN RRAM devices integrated with CMOS (1T1R). k Trench metal-fill. l Optical image of 1T1R devices with filled pseudo-vias ensuring good connectivity between CMOS and RRAM (inset shows SEM imaging of a single fully filled trench). m SEM imaging (52° stage tilt) of FIB-milled CMOS-RRAM cross-sections at the CMOS-RRAM interconnect interface (top) and at the device interface (bottom)
Prior to post-processing, all previously diced CMOS chips underwent an extended O2 plasma (30 min) that dehydrated their surface and removed organic residue. To create RRAM connectivity openings to the top CMOS metal, the chips were first treated with hexamethyldisilazane (HMDS) vapour to enhance photoresist adhesion and then spin-coated at 4000 rpm with positive photoresist, and soft baked (SB) at 115 °C for 90 s. The resulting ~2.3 μm photoresist thickness was optimised for resolving the smallest dimensions of the desired photolithographic pattern, while additionally maintaining integrity as a protective mask through a prolonged etch process. The etch pattern (L1) comprising isolated 1.5 μm wide squares was exposed by optical direct-write lithography (DWL) using a 405 nm light source through a 20X apochromatic objective lens, with an exposure dose of 150 mJ cm−2 and a focal offset of +2.5 μm. Pattern exposure was repeated across all reticles of the diced chips. Layer to layer alignment can be performed globally at multi-reticle level, or locally per individual reticle. This is guided primarily by the alignment tolerance of the lithographic process and the alignment accuracy of the exposure tool. This was followed by a post-exposure bake (PEB) at 115 °C (90 s), photoresist development in 0.26 N developer (60 s) and a hard bake (HB) at 115 °C (90 s). It should be noted that due to the complexity added by the presence of the underlying CMOS BEOL multilayer interconnect stack, all photolithographic processes were first optimised for the desirable pattern fidelity using focus-exposure matrices with the matching post-processing layouts. The chips for this work were sourced from wafers where the passivation was not thinned as previously described. This was only the case when integrating low-density designs such as the one detailed here, where a deep trench surface topology did not affect any subsequent photolithographic steps and processes. Therefore, the full Si3N4/SiO2 stack was etched by RIE in a CHF3/Ar (20/20 sccm gas flow) plasma at 100 W power and 25 mT pressure, to form ~850 nm deep openings. At the expense of a slower etch rate this process produced features with near-vertical sidewalls, exhibited a favourable ( ~ 1:1) dielectric/photoresist selectivity and resulted in no noticeable photoresist reticulation. Finally, the remaining photoresist mask was removed using NMP at 65 °C and the chips were rinsed with isopropyl alcohol (IPA). Figure 3d shows an optical microscopy image of the passivation openings, where the bright white features correspond to the exposed top CMOS metal. A scanning electron microscopy (SEM) image (inset) of one the openings captured at a 30° tilt angle is also presented.
To pattern the BE of the RRAM devices, the chips were first spin-coated at 5000 rpm with image reversal photoresist, followed by a SB at 105 °C (60 s) to produce a 500 nm thick photoresist layer. It should be noted that all photoresist coating steps included preceding sample dehydration and HDMS treatment steps. The BE pattern (L2) comprising right cornered 1, 2 or 5 μm wide tracks was exposed by optical DWL with an exposure dose of 25 mJ cm−2. No other previously detailed DWL parameters were altered. This was followed by an image reversal process consisting of a PEB at 120 °C (120 s) and a blanket ultraviolet (UV) exposure, and finally photoresist development (0.26 N, 60 s) and a brief descum (60 s) by O2 plasma. A 50 nm thick TiN layer was then deposited by DC sputtering from a 99.995% titanium target in a N2 rich (20 sccm gas flow) plasma at 600 W power and 2 mT process pressure (0.06 nm/s deposition rate). Prior to deposition and without breaking vacuum, a brief 100 W Ar mill removed any surface oxide from the exposed CMOS metallisation that would subsequently be capped by the TiN layer. The electrodes were ultimately patterned by photoresist lift-off using NMP at 65 °C and the chips were rinsed with IPA. Figure 3f shows an optical image of a small section of one of the arrays, in this case integrated with 2 μm wide BE features.
A 5 nm thick HfOxNy active layer was then blanket deposited on the chips by ALD as detailed previously for the optimal active layer, and the thickness of the film was determined by in-situ ellipsometry. To re-expose the metal openings (TiN capped BE contact and CMOS metal-4 TE contact placeholder) the chips were first spin-coated at 5000 rpm with 1 μm positive photoresist, followed by a SB at 90 °C (60 s), exposure by optical DWL with a dose of 80 mJ cm−2, PEB at 110 °C (60 s) and photoresist development (0.26 N, 60 s). The layout of the etch pattern (L3) comprising 2 μm wide openings is overlayed to the L1 openings as highlighted by the features in yellow in Fig. 3h. The HfOxNy film was then etched by RIE using the process parameters detailed for the CMOS passivation etch. The remaining photoresist mask was then removed as described previously. The insets of Fig. 3h show magnified UV images of the re-opened connections, with the faint square patterns representing the edges of the newly etched features.
50 nm thick TiN TEs were then fabricated following the procedure detailed for the BE fabrication process. The TE pattern (L4) comprises vertically running 1, 2 or 5 μm wide tracks intersecting the BE pattern. Figure 3j shows an optical image of a section of the 16 × 16 array with 2 × 2 μm2 TiN/HfOxNy/TiN RRAM devices integrated with the CMOS in a 1T1R configuration. It should be noted that it is anticipated that a post-deposition native oxide will form on the surface of the TiN layer, effectively altering the interconnection conductivity of the electrode. To minimise this effect, the TE is normally capped with a thin layer ( ~ 20 nm) of Pt, which is DC sputtered, without breaking vacuum, from a 99.99% platinum target in an Ar rich (20 sccm gas flow) plasma at 400 W power and 3 mT process pressure (0.4 nm/s deposition rate).
To metal-fill the etched trenches, the chips were first spin-coated at 3500 rpm with 3 μm negative photoresist followed by a SB at 105 °C (60 s), exposure by optical DWL using a 365 nm light source and a dose of 155 mJ cm-2, PEB at 105 °C (60 s), photoresist development (0.26 N, 90 s) and a brief descum (60 s) by O2 plasma. The layout of the fill pattern (L5) comprising 4 μm wide squares was overlayed to the L1/3 openings. A 10/850 nm Ti/Al bi-layer with Ti serving as adhesion, was then deposited by e-beam evaporation (0.2/0.6 nm/s deposition rate) at 10−7 Torr (or lower) pressure and finally photoresist lift-off defined the fill pattern. Aluminium was selected as the fill metal, as it is frequently utilised for CMOS interconnect and vias, particularly at the technology node discussed in this article. Copper and tungsten, which offer lower resistivity and enhanced resistance to electromigration, respectively, are compatible options for integration at the 130 nm node and beyond. Figure 3l shows an optical image of the integrated RRAM devices with their CMOS connecting trenches fully filled, while the inset shows a SEM image of a single filled trench. The metal protruding from the chip surface is the section of the pattern extending past the trenches.
To cross-sectionally validate the integration process, focused ion beam (FIB) milling was performed along the CMOS-RRAM interconnect and device interfaces, as can been seen from SEM imaging in Fig. 3m. The integration process appears to have not caused any physical damage to the underlying CMOS BEOL-stack, while the CMOS passivation trenches are homogenously filled with the thick aluminium, and the TiN layer is conformally coated on the sidewalls of the trenches, in a manner similar to a barrier layer. Interestingly enough, the CMOS passivation seems to have been over-etched, and the RIE process has clearly partially attacked the top CMOS metallisation, thus modifying the local topology. However, the etched metal has mostly been recovered through the aluminium deposition, in which case this effect is unlikely to be of any significance. Similarly, SEM imaging through the device cross-section shows that the patterned RRAM stack appears to be homogeneous.
To enable access for wire-bonding or direct electrical probing of the integrated array, a final process was utilised to create openings to the foundry passivated pads. First, the chips were spin-coated at 2000 rpm with 3 μm positive photoresist, followed by a SB at 115 °C (90 s), exposure by optical DWL using a 405 nm light source through a 5X achromatic objective lens with a dose of 200 mJ cm-2, a PEB at 115 °C (90 s) and photoresist development (0.26 N, 60 s). The layout of the pad etch pattern (L6) comprises 57 ×67 μm rectangles, slightly smaller than the foundry designed metal pads. The film was then etched by RIE using the previously detailed passivation etch, with the addition of a brief CF4/O2 finishing etch (60/4 sccm gas flow) at 150 W and 60 mT pressure, which minimises the risk of damaging the metal layer during the pad exposure process. Figure 4a shows an optical image of a standard multi-reticle (3 ×2) chip used in the integration process. The expanded view shows a 1T1R integrated memory array chip with exposed pads for the word-lines, bit-lines, source-lines and FET bulk connections.
The alternative text for this image may have been generated using AI.a Typical integrated multi-reticle chip. Expanded view shows a single fully-integrated CMOS-RRAM die. b Resistance map of array with devices at their pristine state. c Optical image of 16 × 16 1T1R (pMOS-TiN/HfOxNy/TiN) array with highlighted devices selected for electrical characterisation. d Resistance map of array after one electroforming cycle, with most of the (diagonally selected) devices at their operating resistive range. e Representative RRAM forming (1T1R cell (12,12)) and f switching (1T1R cell (3,3)) I–V characteristic curves
To verify that the integration process is not impacting the performance of the CMOS electronics, an on-reticle, standalone nMOS cell was first electrically characterised and optically validated, prior and after undergoing all critical integration processes. Figure S1a presents the measurement setup and a schematic diagram of the device, where the drain of the nMOS is connected to a (foundry-fabricated) 24.8 kΩ polysilicon load, representing the resistance of a conditioned RRAM. Fig. S1b and c show optical imaging of the device before and after post-processing, where the bonding pads of the nMOS cell have been re-opened. The FET’s characteristic I–V curves, as measured before (solid lines) and after post-processing (dashed lines), are shown in Fig. S1d and f, and indicate that the integration process does not affect the CMOS. This can be seen more clearly in Fig. S1e and g, where the offset between the two current measurements is presented as a percentage deviation from the pristine current measurement and is negligible (primarily < 1%).
The integration process was then electronically validated by investigating the forming and switching characteristics of sample 1T1R arrays, using a custom-designed measurement platform (see methods). The basis of the array used as a benchmark platform is configured such that a single gate-driven line (word-line) controls a column of devices and a single source-line controls the biasing of the pMOS that form the core of the circuit. Current read-out is done from the free electrode (TE), ie. the end of the RRAM not directly connected to the pMOS (bit-line). The transistors are 5 V devices and are active low. The voltage supplied to the RRAM is determined by the voltage drop between the drain (Vd: 5–0 V) and the free biasing electrode (VR: -5–5 V) minus the voltage drop across the transistor (Vds), i.e., ΔVR = Vd – VR – Vds. Figure 4b shows a resistance map for a 16 ×16 1T1R array, where all the cells are initially measured (read at 0.5 V) at their pristine state (MΩ range). Figure 4c presents an optical image of a fabricated array where the highlighted devices have undergone an electroforming procedure that conditions them to within their operating resistive range (10–100 kΩ, read at 0.5 V), as can been seen from the resistance map of Fig. 4d (diagonal selection). This consequently allows to manipulate the devices freely, and in this particular case it is typically achieved by applying a set of a 1000 1 ms-wide pulses at voltages ranging from 2 to 3 V although devices can also be formed by applying an I–V curve as shown in Fig. 4e. Similarly, devices can be programmed to different resistive values with either 100 μs pulses ranging from 1–3 V using a scheme similar to32 or directly using I–V sweeps as shown in Fig. 4f.
Figure S2a demonstrates device-to-device variability from 25 integrated RRAM devices that have been randomly selected from several arrays located on a number of multi-reticles. All individual characteristic I–V curves represent the first cycle of a measurement set (at ±1 V, which is below the switching threshold), per device, with the arithmetic mean of all the measurements highlighted. The resistance spread (at 0.5 V) of the electroformed devices across the array is 25–50 kΩ. Similarly, 15 distinct devices, programmed at several resistive states, were randomly selected to perform 240 min-long retention measurements. The results presented in Figure S2b indicate that all devices retain their resistive state throughout this measurement period, demonstrating their analogue non-volatile programmability. Finally, a randomly selected device was used to demonstrate prolonged analogue cycling between a high resistance state (HRS) and a low resistance state (LRS), as shown in Fig. S2c. This was achieved via a pulsing sequence of ± 2.2 V, 1000 µs-wide pulses, with intermediate read measurements at Vread = 0.5 V (see Fig. S2d). These results demonstrate a clear, albeit small resistive offset between the two states, which remains relatively consistent during the cycling procedure. Such small memory window is often desirable for analogue switching, where smoother, gradual changes in resistive states32,35 are employed and can offer prolonged device lifetimes, while maintaining RRAM behaviour.
It should be noted that while this representative electrical characterisation validates the integration strategy and confirms process and technology compatibility, it does not examine integration uniformity and repeatability, and their potential influence to device characteristics. The example resistance map of these formed RRAM cells (Fig. 4d) shows that some of the devices remain at their pristine state. Although unlikely, this could be attributed to local dimensional and thin-film thickness and roughness non-uniformities arising by patterning and process-induced effects that would directly impact device-to-device characteristics. More likely, these variabilities are related to the stochasticity in RRAM filament formation. Typical process-induced variations are likely to be systematic and would not normally be so localised. Such effects can be quantified and potentially correlated to device characteristics, initially at multi-reticle level, at the prototyping stage, and ultimately as standard wafer-level uniformity and repeatability measurements for process control.
To derive an estimate for the overall yield of the integration process, a method that identifies defects during critical process stages is considered. The first stage determines yield for the CMOS passivation etch (RRAM connectivity openings) and this is illustrated in Fig. S3a, which shows optical imaging of 18 etched arrays, located on three multi-reticles. Arrays that have all the openings fully etched, pass, resulting in a 78% yield, while arrays that have one or more openings partially etched fail. Figure S3b clearly differentiates between openings that are fully and partially etched. A method for detecting etched features in optical images has additionally been introduced for automating the inspection process (see Supplementary Material), and the automated yield analysis for one of the arrays (A6MR3) is demonstrated in Fig. S4. The detection method closely matches the findings of the manual analysis, while filtering parameters can be adjusted to further optimise the detection. At the second stage of yield analysis, full-device defects are examined as shown in Fig. S5a. This is demonstrated using six integrated RRAM arrays that have been fabricated from etched arrays that have passed the first-stage yield analysis, with device dimensions ranging from 1 to 5 × 5 µm2. As it would be anticipated, arrays with larger RRAM dimensions are defect-free (albeit for a small sample size), while a ~ 98% yield is determined for the smallest sized arrays. Figure S5b shows that common RRAM fabrication defects appear as loss of connectivity between RRAM and the CMOS or as active area dimensional mismatch between nominal and fabricated devices. It should be noted that as RRAM dimensions (CD and pitch) shrink and array sizes increase, the yield is expected to reduce. This is compounded by the fact that yield is normally derived at wafer-level and from a large sample size. Yields are typically below 50% for early R&D, new processes and technologies, rising up as processes are further developed and ultimately exceed 90% for volume production processes and mature technologies. The combined ~77% two-stage yield, albeit likely an overestimation, validates the integration strategy as an enabling step towards transitioning from R&D to volume production.
The defect-free, 2 × 2 µm2 arrays are finally electrically measured at their pristine state, and resistive statistical distributions and array maps of the devices are presented in Fig. S6. The results show that for 99% of the devices, the measured resistances are primarily narrowly distributed in the MΩ range, while only ~1% of the devices measure kΩ and GΩ resistances. While these outlier measurements could be attributed to defects in the fabrication process that could not be detected during the two-stage yield analysis of the integration process, they may also be the result of the measurement procedure (i.e. devices being electroformed by the low-voltage read operation).
Array up-scaling
While the core processes of the monolithic integration were developed using small, low-density array designs, they are largely transferrable to more complex, large, and high-density memory arrays. Nonetheless, this transition is contingent on several processing factors that should be taken into consideration. For this purpose, we have designed a CMOS-based, RRAM characterisation platform with on-chip programming and read capabilities, comprising 4 identical and independently controlled 512 × 512 sub-arrays that when integrated with RRAM have the capacity to characterise up to 1 million cells44 in a 1T1R configuration. An optical microscopy image of the architecture can be seen in Fig. 5a. Figure S7a shows a layout snippet of a dense 1 µm RRAM electrode configuration, with a 2:1 line-to-space feature ratio through the topology-heavy, CMOS-RRAM interface (dotted line), designed for optical DWL-based processing of the 1Mbit array. The significance of thinning the foundry passivation is evident by comparing the cross-sectional schematics of Fig. S7a, which illustrate the desired electrode photolithographic patterns (photoresist profile), post metallisation, defined both on ~850 nm, deep trench and ~100 nm, shallow trench topologies. Clearly, a deep trench topology is unlikely to support defect-free, high-density patterning, as it is impacted by factors such as locally non-uniform photoresist surface coverage and significant local spatial variations in focal length on the exposure field (beyond the depth of focus). This is compounded by the fact that narrow, deep trench passivation topologies cannot be realised using thin, high-resolution photoresist masks alone, and would require the use of supplementary hard mask layers to enable pattern transfer, thereby introducing added complexity to the integration process. In comparison, a deep trench topology presents little challenge for low-density array patterning as illustrated in Fig. S7b, and previously demonstrated.
The alternative text for this image may have been generated using AI.a Optical microscopy imaging of a 1Mbit 1T1R characterisation platform comprising 4 identical 512 × 512 sub-arrays. Comparison of passivation openings (by RIE) to expose the top CMOS metallisation, patterned by b optical DWL (UV imaging) and c e-beam lithography (SEM imaging). d Magnified optical imaging of a section of the integrated RRAM array (with relative size highlighted within the full array) and e high magnification SEM imaging (30° stage tilt) highlighting a single 1 μm2 RRAM cell
As the density of the RRAM array increases and the minimum CD decreases, the integration methodology is in part informed by the capabilities of the available lithographic technologies. Each of the 4 sub-arrays of the 1Mbit design is laid out such that the top CMOS metal of each row in the sub-array comprises a long track serving as a connection placeholder for a common BE across all RRAM cells in the row, while each column consists of small metal islands that serve as individual connection placeholders for the TE of each RRAM cell in the column. The minimum relevant CD is 500 nm for the width of the metal-4 island, with a pitch of ~2 µm. Figure S8a and b show the layouts for producing CMOS-RRAM connectivity openings, designed both for optical and e-beam DWL, respectively. While the larger BE opening is laid out in the same manner for both lithographic options, this is not the case for the TE openings. The e-beam layout uses 400 nm wide openings, slightly smaller than the underlying metal, while optical patterning, which in comparison is limited in CD and pitch resolution, employs a sparse array layout with larger 1 µm openings that extend beyond the underlying CMOS metal. Both lithographic options were trialled for pattern transfer, with optical DWL following identical procedures and parameters for photoresist coating and exposure, as those detailed for the patterning of the active layer of the 16 ×16 array. For e-beam DWL, the chips were first dipped in a cationic priming agent to enhance resist adhesion, and then rinsed with DI water and baked at 180 °C (5 min). The chips were then spin-coated at 2000 rpm with ~300 nm negative high-contrast e-beam resist, followed by a SB at 150 °C (120 s). The etch pattern was then exposed using a 32 nA beam current with an exposure dose of 342 µC/cm2. This was followed by resist development in amyl acetate (60 s), rinsing with IPA, HB at 130 °C (60 s) and a brief descum by O2 plasma (60 s, 150 W). Multi-reticle substrates with the thinned SiO2 passivation were finally etched by RIE using our standard CHF3/Ar-based plasma process to form ~100 nm deep, and 400 nm or 1 µm wide openings. Figure 5b and c show representative imaging of the passivation openings as defined by the two lithographic options (Fig. S9a shows the larger openings that provide connectivity to the BE). Clearly, the optical DWL-based passivation etch extends beyond the width of the underlying CMOS metal, which to an extent, would normally act as an etch stop, and thus allow for relaxed over-etch process tolerances. Therefore, to minimise over-etching into the underlying ILD-3, the RIE process should be supported by end-point depth-profiling metrology. Figure S8c and d present the layouts for integrating the 3-layer RRAM stack to realise a 0.5Mbit (sparse) 1T1R array with 1 μm2 RRAM or a full 1Mbit 1T1R array with 500 × 500 nm2 RRAM, using optical and e-beam DWL-based integration, respectively. While e-beam DWL-based processing can support the integration of a full-density array, potentially allowing the fabrication of RRAM features with deep-nm dimensions, optical DWL-based processing is in comparison, significantly restricted by the resolution limit of the optics, and is normally unable to resolve the sub-micrometre spacings required for the full-density array implementation. Nevertheless, optical DWL-based processing offers a cost-effective and rapid-prototyping route, which at early-stage development and when employed with resolution enhancement techniques, is often sufficient for demonstrating proof-of-concept (subset) integration of complex and dense array designs.
We demonstrate RRAM integration using our optional oxynitride-based (Pt/TiOxNy/Pt, 10/10/20 nm thickness) material stack, which in-part explores the utilisation of alternative layer deposition and processing techniques. Platinum RRAM electrodes were deposited by evaporation (0.06 nm/s deposition rate) at 10-7 Torr (or lower) pressure, while the TiOxNy active layer was deposited by DC sputtering using process parameters that have been previously detailed. The BEs of the RRAM, which comprise long tracks spanning a full row of devices (common per row), were patterned by lift-off (see Fig. S9b), using the methodology that has been previously described. The active layer was in this case, also patterned by lift-off (see Fig. S9c), owing to the fact that sputtering produces, in comparison, less conformal films than the highly-conformal ALD process. This, in turn, enables for defect-free (fencing artefacts) lift-off patterning, which would otherwise be difficult to attain, even when employing highly undercut photoresist patterns. At half-array density, the patterning process for the TE features of the RRAM remains challenging for this photolithographic approach. To produce the desired pattern, we utilise double patterning, a well-established resolution enhancement technique that has been successfully implemented using several methodologies. In this case, by exploiting the fact that the alignment accuracy of the available photolithographic technology surpasses the minimum CD resolution, the half-array is fabricated using a two-step process, wherein the smallest feature size is realised as a cumulative outcome of both processes, rather than being resolved in a single step, as can been seen from the optical images of Fig. S9c and d. Finally, Fig. 5d shows an optical image of a larger section of the integrated 0.5Mbit 1T1R array (on-chip circle represents the actual size relative to full chip), while high magnification SEM imaging in Fig. 5e highlights a single 1 μm2 RRAM cell, with the trench revealing the interface between CMOS BEOL and RRAM. The CMOS metal-4 island protruding within the trench is an indication that in this case the passivation has been slightly over-etched into the ILD-3.
Applications-focused CMOS-RRAM Architectures
Ultimately, integrated RRAM technologies can coexist with and enhance a plethora of CMOS-based architectures to realise systems that offer several pathways towards a beyond-Moore era. Although the challenges of RRAM integration are to some extent associated with the specific CMOS architecture being integrated with (i.e., developing RRAM technologies with targeted specifications), the proposed integration strategy and core fabrication processes are architecture-agnostic. The development and realisation of high-density arrays practically represents the peak in monolithic-integration complexity, which in turn, then provides the platform for transferring the same methodologies, technologies and processes to any proposed architecture. Example architectures are demonstrated in Fig. 6, which shows optical microscopy images of several application-focused RRAM-enabled CMOS chips, using TiN/HfOxNy/TiN (50/5/50 nm) RRAM with dimensions ranging from 1 to 2 × 2 μm2. The RRAM cells were designed and populated in a manner that meets the specifications and BEOL layout of each architecture. These architectures include a 1T1R multi-function sensor interface for neuromorphic and bio-inspired analysis45, a 9T4R analogue content addressable memory for analogue template matching at the edge46, an analogue domain aggregator system for neural network accelerators47, and 1T1R and 2T1R radiation-hardened (total ionisation dose and single-event effects) memory cells, to determine radiation tolerance within functional memory arrays, for use in high-radiation environments48. All architectures have been integrated with RRAM devices using the methodology and fabrication processes detailed in this article.
The alternative text for this image may have been generated using AI.